TM 10-6665-297-13&P
1-3.1.5 Alarm Circuit. (Figure 1-10) The alarm circuit is identical to the warn- ing circuit described above
except that the reference voltage representing the level at which the alarm circuit operates is set with
ALARM potentiometer R28 and compared in amplifier U5 for CD800/830, or R41 and U3 for
CD802/832. Signals over reference level turn on transistor Q6 for CD800/830 or Q3/Q4 for CD802/832
to send power from the fail relay through the alarm relay and front panel red ALARM light. The alarm
potentiometer (R28 for CD800/830 or R41 for CD802/832) is normally set to provide a reference
voltage equivalent to 40-percent L. E. L. Once tripped, the warning and alarm relays remain in the
energized state until the ALARM RESET pushbutton is depressed to reopen the relay latching circuit.
1-3.1.6 Delay Circuits. (Figures 1-10, 1-11)
NOTE:
TO
PROTECT
AGAINST
TRANSIENT
VOLTAGE
IMBALANCES DURING WARMUP, DELAY CIRCUITRY
INHIBITS WARNING, ALARM, AND TEST RESPONSES FOR
FROM 15 to 45 SECONDS AFTER POWER IS APPLIED,
EVEN IF POWER INTERRUPTIONS HAVE BEEN BRIEF.
During the brief warmup period after power has been applied, circuit imbalances could generate false
warning and alarm signals. Therefore a nominal 15-to-45-second delay circuit is provided to inhibit such
signals until the proper operating temperature at the detector is reached. Further, two identical 2-
second (nominal) delay circuits--one for the warning circuit (Figure 1-10, CD800/830; Figure 1-11,
CD802/832), and the other for the alarm circuit (not shown)--act to inhibit transient pulses caused by
any temporary circuit disturbances, so that only signals sustained beyond the brief period of delay are
permitted to energize the warn and alarm relays.
For CD800/830 control modules, the nominal 45-second delay occurs between resistor R44 and
capacitor C3. Capacitor C3 takes time to charge through R44, depriving the emitters of unijunction
transistors Q1 and Q3 of positive forward-biased (turn-on) voltage. Q1 and Q3 therefore cannot trigger,
in turn depriving silicon-controlled rectifiers Q2 and Q4 of positive bias voltages which would cause
these rectifiers to conduct. Since warning and alarm signals must pass through Q2 and Q4 respectively
to energize the warning or alarm relays, no warning or alarm signals can reach the relays until capacitor
C3 is charged.
The CD802/832 15-to-25-second delay occurs between resistor R56 and capacitor C9, depriving silicon-
controlled rectifier SR3 of bias, which causes transistors Q3, Q4, and Q5 to be nonconducting so that warning
and alarm relays cannot be switched during the period of delay.
For CD800/830 control modules, after capacitor C3 is charged (and detector operating voltages have been
reached), the further 2-second delay to block reactions to spurious pulses occurs between resistor R3 and
capaci-
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7/1/76
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